freebsd:freebsd_-_prozessor-microcode-update
Unterschiede
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| freebsd:freebsd_-_prozessor-microcode-update [2020-11-20 09:52:36] – manfred | freebsd:freebsd_-_prozessor-microcode-update [2025-08-10 01:34:02] (aktuell) – manfred | ||
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| + | ====== FreeBSD - Prozessor-Microcode-Update ====== | ||
| + | |||
| + | [[https:// | ||
| + | |||
| + | |||
| + | ===== FreeBSD 12.1 ===== | ||
| + | |||
| + | |||
| + | ==== Installation von cpupdate ==== | ||
| + | |||
| + | '' | ||
| + | > portsnap auto | ||
| + | ... | ||
| + | Building new INDEX files... done. | ||
| + | | ||
| + | > cd /usr/ports | ||
| + | > make search name=cpupdate | ||
| + | Port: | ||
| + | Path: / | ||
| + | Info: CPU microcode update utility for x86 | ||
| + | Maint: | ||
| + | B-deps: | ||
| + | R-deps: | ||
| + | WWW: https:// | ||
| + | | ||
| + | > cd / | ||
| + | > make clean | ||
| + | > make config-recursive | ||
| + | > make | ||
| + | > make install | ||
| + | > make install-microcodes | ||
| + | |||
| + | '' | ||
| + | > kldload cpuctl | ||
| + | > kldstat | fgrep cpuctl | ||
| + | | ||
| + | > echo ' | ||
| + | |||
| + | > echo ' | ||
| + | |||
| + | |||
| + | ==== CPU-Überprüfung vor dem Patch ==== | ||
| + | |||
| + | CPU-Microcode-Infos: | ||
| + | > cpupdate -i | ||
| + | Found CPU(s) from Intel | ||
| + | Core 0 to 11: CPUID: a0653 Fam 06 Mod a5 Step 03 Flag 02 uCode 000000cc | ||
| + | |||
| + | ...es ist dieses CPU-Modell: "Fam 06 Mod a5 Step 03", demnach ist der Patch mit dem Namen '' | ||
| + | |||
| + | Aktuell (// | ||
| + | |||
| + | <file bash> | ||
| + | # / | ||
| + | Spectre and Meltdown mitigation detection tool v0.37+ | ||
| + | |||
| + | Checking for vulnerabilities on current system | ||
| + | Kernel is FreeBSD 12.1-RELEASE-p10 FreeBSD 12.1-RELEASE-p10 #6 r366792M: Sun Oct 18 15:17:47 MEST 2020 | ||
| + | CPU is Intel(R) Core(TM) i5-10600T CPU @ 2.40GHz | ||
| + | |||
| + | Hardware check | ||
| + | * Hardware support (CPU microcode) for mitigation techniques | ||
| + | * Indirect Branch Restricted Speculation (IBRS) | ||
| + | * SPEC_CTRL MSR is available: | ||
| + | * CPU indicates IBRS capability: | ||
| + | * Indirect Branch Prediction Barrier (IBPB) | ||
| + | * PRED_CMD MSR is available: | ||
| + | * CPU indicates IBPB capability: | ||
| + | * Single Thread Indirect Branch Predictors (STIBP) | ||
| + | * SPEC_CTRL MSR is available: | ||
| + | * CPU indicates STIBP capability: | ||
| + | * Enhanced IBRS (IBRS_ALL) | ||
| + | * CPU indicates ARCH_CAPABILITIES MSR availability: | ||
| + | * ARCH_CAPABILITIES MSR advertises IBRS_ALL capability: | ||
| + | / | ||
| + | | ||
| + | * CPU explicitly indicates not being vulnerable to Meltdown (RDCL_NO): | ||
| + | * CPU microcode is known to cause stability problems: | ||
| + | * CPU vulnerability to the three speculative execution attack variants | ||
| + | * Vulnerable to Variant 1: YES | ||
| + | * Vulnerable to Variant 2: YES | ||
| + | * Vulnerable to Variant 3: NO | ||
| + | |||
| + | CVE-2017-5753 [bounds check bypass] aka ' | ||
| + | > STATUS: | ||
| + | |||
| + | CVE-2017-5715 [branch target injection] aka ' | ||
| + | * Mitigation 1 | ||
| + | * Kernel supports IBRS: YES | ||
| + | * IBRS enabled and active: | ||
| + | * Mitigation 2 | ||
| + | * Kernel compiled with RETPOLINE: | ||
| + | > STATUS: | ||
| + | |||
| + | > How to fix: To enable IBRS, use `sysctl hw.ibrs_disable=0` | ||
| + | |||
| + | CVE-2017-5754 [rogue data cache load] aka ' | ||
| + | * Kernel supports Page Table Isolation (PTI): | ||
| + | * PTI enabled and active: | ||
| + | * Reduced performance impact of PTI: YES (CPU supports INVPCID, performance impact of PTI will be greatly reduced) | ||
| + | > STATUS: | ||
| + | |||
| + | A false sense of security is worse than no security at all, see --disclaimer | ||
| + | </ | ||
| + | |||
| + | |||
| + | ==== CPU-Überprüfung nach dem Patch ==== | ||
| + | |||
| + | > / | ||
| + | Starting cpupdate. | ||
| + | Found CPU(s) from Intel | ||
| + | No updating error. Registering CPU features | ||
| + | Successfully registered new CPU features | ||
| + | hw.ibrs_disable: | ||
| + | |||
| + | CPU-Microcode-Infos: | ||
| + | > cpupdate -i | ||
| + | Found CPU(s) from Intel | ||
| + | Core 0 to 11: CPUID: a0653 Fam 06 Mod a5 Step 03 Flag 02 uCode 000000e0 | ||
| + | |||
| + | Jetzt (// | ||
| + | |||
| + | <file bash> | ||
| + | # / | ||
| + | Spectre and Meltdown mitigation detection tool v0.37+ | ||
| + | |||
| + | Checking for vulnerabilities on current system | ||
| + | Kernel is FreeBSD 12.1-RELEASE-p10 FreeBSD 12.1-RELEASE-p10 #6 r366792M: Sun Oct 18 15:17:47 MEST 2020 | ||
| + | CPU is Intel(R) Core(TM) i5-10600T CPU @ 2.40GHz | ||
| + | |||
| + | Hardware check | ||
| + | * Hardware support (CPU microcode) for mitigation techniques | ||
| + | * Indirect Branch Restricted Speculation (IBRS) | ||
| + | * SPEC_CTRL MSR is available: | ||
| + | * CPU indicates IBRS capability: | ||
| + | * Indirect Branch Prediction Barrier (IBPB) | ||
| + | * PRED_CMD MSR is available: | ||
| + | * CPU indicates IBPB capability: | ||
| + | * Single Thread Indirect Branch Predictors (STIBP) | ||
| + | * SPEC_CTRL MSR is available: | ||
| + | * CPU indicates STIBP capability: | ||
| + | * Enhanced IBRS (IBRS_ALL) | ||
| + | * CPU indicates ARCH_CAPABILITIES MSR availability: | ||
| + | * ARCH_CAPABILITIES MSR advertises IBRS_ALL capability: | ||
| + | / | ||
| + | | ||
| + | * CPU explicitly indicates not being vulnerable to Meltdown (RDCL_NO): | ||
| + | * CPU microcode is known to cause stability problems: | ||
| + | * CPU vulnerability to the three speculative execution attack variants | ||
| + | * Vulnerable to Variant 1: YES | ||
| + | * Vulnerable to Variant 2: YES | ||
| + | * Vulnerable to Variant 3: NO | ||
| + | |||
| + | CVE-2017-5753 [bounds check bypass] aka ' | ||
| + | > STATUS: | ||
| + | |||
| + | CVE-2017-5715 [branch target injection] aka ' | ||
| + | * Mitigation 1 | ||
| + | * Kernel supports IBRS: YES | ||
| + | * IBRS enabled and active: | ||
| + | * Mitigation 2 | ||
| + | * Kernel compiled with RETPOLINE: | ||
| + | > STATUS: | ||
| + | |||
| + | > How to fix: The microcode of your CPU needs to be upgraded to be able to use IBRS. Availability of a microcode update for you CPU model depends on your CPU vendor. | ||
| + | You can usually find out online if a microcode update is available for your CPU by searching for your CPUID (indicated in the Hardware Check section). | ||
| + | To do a microcode update, you can search the ports for the `cpupdate` tool. Microcode updates done this way are not reboot-proof, | ||
| + | so be sure to do it every time the system boots up. | ||
| + | |||
| + | CVE-2017-5754 [rogue data cache load] aka ' | ||
| + | * Kernel supports Page Table Isolation (PTI): | ||
| + | * PTI enabled and active: | ||
| + | * Reduced performance impact of PTI: YES (CPU supports INVPCID, performance impact of PTI will be greatly reduced) | ||
| + | > STATUS: | ||
| + | |||
| + | A false sense of security is worse than no security at all, see --disclaimer | ||
| + | </ | ||
| + | |||
